Port pin architecture of 8051

GPIO configuration is the first step to learn for the beginners. When we start learning any micro-controller, it becomes essential to understand how to access pins of a particular micro-controller. Many micro-controller has multiple functions to be performed by separate pins. Its construction, access mechanism etc. vary from controller to controller. In this article, we will understand architecture of 8051 port pins.

8051 has four ports named as P0, P1, P2 & P3. Each port has 8 pins. In general, pins are identified as PX.Y where X is port number and Y is pin number ranging from 0 to 7 where 0 indicates LSB and 7 indicates MSB. Thus P0.0 is LSB of port0 and P2.7 is MSB of port2. 8051 architecture supports bit operations also means we can access individual pins of any port instead of accessing entire port at a time.

In 8051, port P0 is open collector port. Remaining ports P1, P2 and P3 has inbuilt pull-up. Architecture of 8051 pins is as shown below.


Port0 has dual functionality. Either it can be used as bi-directional GPIO port or it can be used for memory interfacing. Function of Port0 is selected by control signal as shown in image below. If the control signal is ‘0’, port can be used as GPIO.  To use Port0 for memory interfacing, control signal has to be logic ‘1’.

Architecture of Port0

Architecture of Port0

First let us understand use of Port0 as GPIO Port.

PORT0 as Input Port:

To access Port0 as input port, control signal has to be logic 0. Along with 1 has to be written to the latch. When we write logic 1 to the latch, both MOSFET are turned off hence when we apply read pin signal, status of input pin is available on internal bus.



PORT0 as Output Port:

If we write logic 1 to latch, lower MOSFET is turned off. Because of logic 0 at control signal, upper MOSFET is also turned off. As we have written logic 1, we expect logic 1 at output but we get floating point because both the MOSFET are turned off. We need to use Pull-Up resistor as shown in fig to get logic 1.



If we want to write logic 0 on port pin, when we write 0 on latch, lower MOSFET is turned ON which makes the pin shorted to ground providing logic 0 as output.

PORT0 for memory interfacing:

When we use Port0 for memory interfacing, control signal is logic 1. MOSFET are driven by signal address/data pin. If address/data pin is at logic 0, lower MOSFET is ON and upper MOSFET is OFF. Hence pin is grounded via lower MOSFET. When address/data pin is at logic 1, lower MOSFET is OFF and upper MOSFET is ON. Hence output is connected with Vcc via upper MOSFET. Thus Pull-Up resistor is not required for memory interfacing.


Construction of Port1

Construction of Port1

Port1 is used as GPIO only. Unlike Port0, Port1 has internal pull-up resistor. When used as output port, it is pulled-up or down as per the value written on latch pin. When we want to use it as input pin, we write logic 1 to latch. Hence the MOSFET is turned off. Input signal is available on internal bus when read pin signal has been applied.


The structure of Port2 is as shown in image.

Construction of Port2

Construction of Port2

Port2 is used as higher order address bus for external memory interfacing. I/O operation is similar to Port1 as explained earlier. When used as address bus, pins are driven by the address bus signal as shown in image.


Port3 has alternate functions on each pin. Structure of Port3 is as shown in image.

Construction of Port3

Construction of Port3

Its IO operation is same as Port1 explained earlier. However alternate functions on all pins makes it different from other ports. Alternate functions of Port3 is as mentioned below.

Port Pin Alternate Function
P3.0 RxD
P3.1 TxD
P3.2 INT0
P3.3 INT1
P3.4 T0
P3.5 T1
P3.6 WR
P3.7 RD

We will discuss more about alternate functions in other tutorials later on.

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